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PADC09QJ1300AAV ACTIVE

Automotive, quad-channel, 9-bit, 1.3-GSPS, analog-to-digital converter (ADC) with JESD204C interface

Inventory: 28
 

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Packaging information

Package | Pins Package qty | Carrier Operating temperature range (°C)
FCBGA (AAV) | 144 168 | JEDEC TRAY (5+1)
-40 to 125
Package | Pins FCBGA (AAV) | 144
Package qty | Carrier 168 | JEDEC TRAY (5+1)
Operating temperature range (°C) -40 to 125
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Features for the ADC09QJ1300-Q1

  • Qualified for automotive applications
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3GSPS
    • Non-interleaved architecture
    • Internal dither reduceshigh-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 53.5 dBFS
    • ENOB (100 MHz): 8.5Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –143dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDeslanes
    • Maximum linerate: 17.16 Gbps
    • 64B/66B and 8B/10Bencoding modes
    • Subclass-1 support for deterministiclatency
    • Compatible with JESD204Breceivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO
    • VCO frequency: 7.2–8.2GHz
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clockfor SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS): 435 mW / channel
  • Power supplies: 1.1 V, 1.9 V
  • Create a custom design for the ADC09QJ1300-Q1 with the WEBENCH® Power Designer

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Description for the ADC09QJ1300-Q1

ADC09QJ1300-Q1 is a quad channel, 9-bit, 1.3 GSPSanalog-to-digital converter (ADC). Low power consumption, high sampling rate and 9-bit resolutionmakes the ADC09QJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systemsand handheld test equipment. ADC09QJ1300-Q1 qualified for automotiveapplications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response forfrequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response forpulse-based systems. The full-power input bandwidth also enables direct RF sampling ofup to 4GHz.

A number of clocking features are included to relax system hardware requirements, such asan internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generatethe sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA orASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printedcircuit board (PCB) routing. Interface modes support from 2 to 8 lanes and SerDes linerates up to 17.16 Gbps to allow theoptimal configuration for each application.

Pricing


Qty Price (USD)
1-99 930.32
100-249 842.1
250-999 818.04
1,000+ 802.0