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RF-sampling 12-bit ADC with dual 5.2-GSPS or single 10.4-GSPS

Availability: 27


Package | PIN: FCBGA (AAV) | 144
Temp: I (-40 to 85)
Package qty | Carrier: 168 | JEDEC TRAY (5+1)
Qty Price
1+ $2,451.68


  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, VFS = 1.0VPP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.4 dBFS/Hz
    • ENOB (dual channel,FIN = 2.4 GHz): 8.6Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable inputfrequency range: > 10 GHz
    • Full-scale input voltage(VFS, default): 0.8 VPP
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifiessynchronization and interleaving
    • Temperature and voltage invariantdelays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for samplemarking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64B/66B and8B/10B encoding
    • 8B/10B modes are JESD204Bcompatible
  • Optional digital down-converters (DDC):
    • 4x and 8x complex decimation
    • Four independent 32-Bit NCOsper DDC
  • Power consumption: 4.0 W
  • Power supplies: 1.1 V, 1.9 V

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Texas Instruments  PADC12DJ5200RFAAV

The ADC12DJ5200RF device is an RF-sampling, giga-sample, analog-to-digitalconverter (ADC) that can directly sample input frequencies from DC to above 10 GHz.ADC12DJ5200RF can be configured as a dual-channel, 5.2 GSPSADC or single-channel, 10.4 GSPS ADC. These operating modes allow programmable tradeoffs in channelcount and Nyquist bandwidth allows for flexible hardware that meets the needs of multipleapplications. Useable input frequency range of up to 10 GHz enables direct RF sampling of L-band,S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-devicesynchronization is supported through JESD204C subclass-1. The JESD204C interface can be configuredto trade-off line rate and number of lanes. Both 8B/10B and 64B/66B data encoding schemes aresupported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates.The interface is backwards compatible with JESD204B receivers when using 8B/10B encoding modes.

Innovative synchronization features, including noiseless aperture delay(TAD) adjustment and SYSREF windowing, simplify system design formulti-channel applications. Optional digital down converters (DDCs) are available to providedigital conversion to baseband and to reduce the interface rate.