text.skipToContent text.skipToNavigation


Automotive single-bit dual-supply bus transceiver

Availability: 9,930


Package | PIN: USON (DRY) | 6
Temp: Q (-40 to 125)
Package qty | Carrier: 5,000 | LARGE T&R
Qty Price
1-99 $0.45
100-249 $0.38
250-999 $0.24
1,000+ $0.16


  • AEC-Q100 Qualified for automotive applications
  • Fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Glitch-free power supply sequencing
  • Maximum quiescent current (ICCA + ICCB) of 10 µA (85°C maximum) and 16 µA (125°C maximum)
  • Up to 500-Mbps support when translating from 1.8 to 3.3 V
  • VCC isolation feature
    • If Either VCC input is below 100 mV, all I/O outputsare disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 8000-V Human body model
    • 1000-V Charged-devicemodel

All trademarks are the property of their respective owners.

Texas Instruments  PCAXC1T45QDRYRQ1

The SN74AXC1T45-Q1 is AEC-Q100 qualified single-bit non-inverting bus transceiver thatuses two individually configurable power-supply rails. The device is operational with bothVCCA and VCCB supplies as low as 0.65 V. The A portis designed to track VCCA, which accepts any supply voltage from 0.65 V to3.6 V. The B port is designed to track VCCB, which also accepts any supplyvoltage from 0.65 V to 3.6 V. Additionally, the SN74AXC1T45-Q1 is compatible with a single-supplysystem.

The DIR pin determines the direction of signal propagation. With the DIR pin configuredHIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B toPort A. The DIR pin is referenced to VCCA, meaning that its logic-high andlogic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using theIoff current. The Ioff protection circuitry ensuresthat no excessive current is drawn from or to an input, output, or combined I/O that is biased to aspecific voltage while the device is powered down.

The VCC isolation feature ensures that if eitherVCCA or VCCB is less than 100 mV, both I/O portsenter a high-impedance state by disabling their outputs.

Glitch-free power supply sequencing allows either supply rail to be powered on or off inany order while providing robust power sequencing performance.