|Package | PIN:||UQFN (RSV) | 16|
|Temp:||Q (-40 to 125)|
|Package qty | Carrier:||
3,000 | LARGE T&R
- AEC-Q100 Qualified for automotive applications
- Fully-configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
- Operating temperature from –40°C to +125°C
- Multiple direction control pins to allow simultaneous up-and-down translation
- Glitch-free power supply sequencing
- Up to 380 Mbps support when translating from 1.8 V to 3.3 V
- VCC Isolation feature
- If either VCC input is below 100 mV, all I/O outputsare disabled and become high impedance
- Ioff Supports partial-power-down mode operation
- Compatible with AVC-family level shifters
- Latch-up performance exceeds 100 mA per JESD 78, Class II
- ESD Protection exceeds JEDEC JS-001
- 8000-V Human-body model
- 1000-V Charged-device model
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Texas Instruments PCAXC4T245QRSVRQ1
The SN74AXC4T245-Q1 AEC-Q100 qualified device is a four-bit non-inverting bus transceiverthat uses two individually configurable power-supply rails. The device is operational with bothVCCA and VCCB supplies as low as 0.65 V. The A portis designed to track VCCA, which accepts any supply voltage from 0.65 V to3.6 V. The B port is designed to track VCCB, which also accepts any supplyvoltage from 0.65 V to 3.6 V. Additionally the SN74AXC4T245-Q1 is compatible with a single-supplysystem.
The SN74AXC4T245-Q1 device is designed for asynchronous communication between data buses.The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending onthe logic level of the direction-control inputs (1DIR and 2DIR). The output-enable inputs(1OE and 2OE) are used to disable the outputs so thebuses are effectively isolated. The SN74AXC4T245-Q1 device is designed so the control pins (xDIRand xOE) are referenced to VCCA.
To ensure the high-impedance state of the level shifter I/Os during power up or powerdown, the xOE pins should be tied to VCCA through apull-up resistor.
This device is fully specified for partial-power-down applications using theIoff current. The Ioff protection circuitry ensuresthat no excessive current is drawn from or to an input, output, or combined I/O that is biased to aspecific voltage while the device is powered down.
The VCC isolation feature ensures that if eitherVCCA or VCCB is less than 100 mV, both I/O portsenter a high-impedance state by disabling their outputs.
Glitch-Free power supply sequencing allows either supply rail to be powered on or off inany order while providing robust power sequencing performance.