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PDRV8350SRTV

100-V Three-Phase Smart Gate Driver

Packaging

Package | PIN: WQFN (RTV) | 32
Temp: Q (-40 to 125)
Carrier: Cut Tape
Qty Price
1-9 $3.76
10-24 $3.39
25-99 $3.16
100-249 $2.77
250-499 $2.59
500-749 $2.20
750-999 $1.86
1000+ $1.78

Features

  • 9 to 100-V, Triple Half-Bridge Gate Driver
    • Optional Integrated Buck Regulator
    • Optional Triple Low-Side Current ShuntAmplifiers
  • Smart Gate Drive Architecture
    • Adjustable Slew Rate Control For EMIPerformance
    • VGS Handshake and Minimum Dead-TimeInsertion to Prevent Shoot-Through
    • 50-mA to 1-A Peak Source Current
    • 100-mA to 2-A Peak Sink Current
    • dV/dt Mitigation ThroughStrong Pulldown
  • Integrated Gate Driver Power Supplies
    • High-Side Doubler Charge Pump For 100% PWM Duty CycleControl
    • Low-Side LinearRegulator
  • Integrated LM5008A Buck Regulator
    • 6 to 95-V Operating Voltage Range
    • 2.5 to 75-V,350-mA Output Capability
  • Integrated Triple Current Shunt Amplifiers
    • Adjustable Gain (5, 10, 20, 40V/V)
    • Bidirectional or UnidirectionalSupport
  • 6x, 3x, 1x, and Independent PWM Modes
    • Supports 120° Sensored Operation
  • SPI or Hardware Interface Available
  • Low-Power Sleep Mode (20 µA at VVM = 48-V)
  • Integrated Protection Features
    • VM UndervoltageLockout (UVLO)
    • Gate Drive Supply Undervoltage (GDUV)
    • MOSFETVDS Overcurrent Protection (OCP)
    • MOSFET Shoot-Through Prevention
    • Gate Driver Fault(GDF)
    • Thermal Warning and Shutdown (OTW/OTSD)
    • FaultCondition Indicator (nFAULT)

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Texas Instruments  PDRV8350SRTV

The DRV835x family of devices are highly-integrated gate drivers for three-phasebrushless DC (BLDC) motor applications. These applications include field-oriented control (FOC),sinusoidal current control, and trapezoidal current control of BLDC motors. The device variantsprovide optional integrated current shunt amplifiers to support different motor control schemes anda buck regulator to power the gate driver or external controller.

The DRV835x uses smart gate drive (SGD) architecture to decrease the number of externalcomponents that are typically necessary for MOSFET slew rate control and protection circuits. TheSGD architecture also optimizes dead time to prevent shoot-through conditions, provides flexibilityin decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects againstgate short circuit conditions through VGS monitors. A strong gate pulldowncircuit helps prevent unwanted dV/dt parasitic gate turn on events

Various PWM control modes (6x, 3x, 1x, and independent) are supported for simpleinterfacing to the external controller. These modes can decrease the number of outputs required ofthe controller for the motor driver PWM control signals. This family of devices also includes 1xPWM mode for simple sensored trapezoidal control of a BLDC motor by using an internal blockcommutation table.