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PSN65LVDS93CTDGGQ1

10-MHz to 135-MHz automotive 28-bit flat-panel display link LVDS SerDes transmitter

Packaging

Package | PIN: TSSOP (DGG) | 56
Temp: T (-40 to 105)
Carrier: Partial Tube
Qty Price
1-9 $9.97
10-24 $8.97
25-99 $8.38
100-249 $7.51
250-499 $7.01
500-749 $6.10
750-999 $5.28
1000+ $5.18

Features

  • AEC-Q100 qualified for automotive applications
    • Temperaturegrade 2: –40°C to 105°C
  • LVDS display series interfaces directly to LCD display panels with integrated LVDS
  • Available in 14-mm × 6.1-mm TSSOP package
  • 1.8-V up to 3.3-V tolerant data inputs to connect directly to low-power, low-voltage applications and graphic processors
  • Transfer rate up to 135 Mpps (Megapixels per second)
  • Pixel clock frequency range 10 MHz to 135 MHz
  • Suited for display resolutions ranging from HVGA up to HD with low EMI
  • Operates from a single 3.3-V supply and 170 mW (typical) at 75 MHz
  • 28 data channels plus clock in low-voltage TTL to four data channels plus clock out low-voltage differential
  • Consumes less than 1 mW when disabled
  • Selectable rising or falling clock edge triggered inputs
  • Support spread spectrum clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and DaVinci™ application processors

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Texas Instruments  PSN65LVDS93CTDGGQ1

The SN65LVDS93C-Q1 FlatLink™ transmitter contains four 7-bit, parallel-load serial-outshift registers, a 7X clock synthesizer, and five low-voltage differential signaling (LVDS) linedrivers in a single integrated circuit. The device can synchronously transmit 28 bits ofsingle-ended, low-voltage transistor-transistor logic (LVTTL) data over five balanced-pairconductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with an integrated LVDS receiver.

When transmitting, the SN65LVDS93C-Q1 loads data bits D0 through D27 into registers onthe edge of the input clock signal (CLKIN). The user can select the rising or falling edge of theclock through the clock select (CLKSEL) pin to ensure compatibility with both rising edge andfalling edge receivers. The frequency of CLKIN is multiplied seven times and then used to releasethe data registers in 7-bit serial streams. The four serial streams and a phase-locked clock(CLKOUT) will output to the LVDS output drivers. The frequency of CLKOUT is the same as the inputclock (CLKIN).

The SN65LVDS93C-Q1 requires no external components and little-to-no usercontrol. The data bus shows the user the full data transmission of the device, from the input tothe transmitter to output of the receiver. The user can input a high level or low level on theCLKSEL pin to select a clock rising or falling edge during this process, or use the Shutdown/Clear(SHTDN) active-low input to inhibit the clock and shut off the LVDS outputdrivers for lower power consumption. A low level on this signal clears all internal registers tolow level.

The SN65LVDS93C-Q1 is characterized for operation over ambient airtemperatures of –40°C to 105°C.