|Package | PIN:||SOIC (DW) | 16|
|Temp:||Q (-40 to 125)|
|Package qty | Carrier:||
2,000 | LARGE T&R
- 5.7-kVRMS single channel isolated gate driver
- AEC-Q100 qualified for automotive applications
- SiC MOSFETs and IGBTs up to 2121 Vpk
- 33-V maximum output drive voltage (VDD-VEE)
- ±10-A drive strength and split output
- 150-V/ns minimum CMTI
- 200-ns response time fast overcurrent protection
- External active miller clamp
- 900-mA soft turn-off when fault happens
- ASC input on isolated side to turn on power switch during system fault
- Alarm FLT on over current and reset from RST/EN
- Fast enable/disable response on RST/EN
- Reject <40-ns noise transient and pulse on input pins
- 12V VDD UVLO and -3V VEE UVLO with power good on RDY
- Inputs/outputs with over/under-shoot transient voltage Immunity up to 5 V
- 130-ns (maximum) propagation delay and 30-ns (maximum) pulse/part skew
- SOIC-16 DW package with creepage and clearance distance > 8 mm
- Operating junction temperature –40°C to 150°C
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Texas Instruments PUCC21736QDWRQ1
The UCC21736-Q1 is a galvanic isolated singlechannel gate driver designed for SiC MOSFETs and IGBTs up to 2121-V DC operating voltage withadvanced protection features, best-in-class dynamic performance and robustness.UCC21736-Q1 has up to ±10-A peak source and sink current.
The input side is isolated from the output side with SiO2capacitive isolation technology, supporting up to 1.5-kVRMS working voltage,12.8-kVPK surge immunity with longer than 40 years Isolation barrier life,as well as providing low part-to-part skew, >150V/ns common mode noiseimmunity (CMTI).
The UCC21736-Q1 includes thestate-of-art protection features, such as fast overcurrent and short circuit detection, shuntcurrent sensing support, fault reporting, active miller clamp, input and output side power supplyUVLO to optimize SiC and IGBT switching behavior and robustness. The ASC feature can be utilized toforce ON power switch during system failure events, further increasing the drivers versatility andsimplifying the system design effort, size and cost.