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SN65LVDS117DGG ACTIVE

Dual 8-port LVDS repeater

Same as: SN65LVDS117DGGG4   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

US ECCN: EAR99 US/Local Export Classification Number

Inventory: 515  
 

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-2-260C-1 YEAR
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (°C)
TSSOP (DGG) | 64 25 | TUBE
-40 to 85
Package | Pins TSSOP (DGG) | 64
Package qty | Carrier: 25 | TUBE
Operating temperature range (°C) -40 to 85
View TI packaging information

Features for the SN65LVDS117

  • Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
  • Outputs Arranged in Pairs From Each Bank
  • Enabling Logic Allows Individual Control of Each Driver Output Pair, Plus All Outputs
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load
  • Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks
  • Propagation Delay Times < 4.5 ns
  • Output Skew Less Than 550 psBank Skew Less Than150 ps Part-to-Part Skew Less Than 1.5 ns
  • Total Power Dissipation Typically <500 mW With All Ports Enabled and at 200 MHz
  • Driver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC < 1.5 V
  • Bus-Pin ESD Protection Exceeds 12 kV
  • Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch

Description for the SN65LVDS117

The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four ('109) or eight ('117) differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.

The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The intended application of these devices, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock and data distribution trees.

The SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.

Pricing


Qty Price (USD)
1-99 9.848
100-249 8.028
250-999 6.31
1,000+ 5.352

Additional package qty | carrier options

Package qty | Carrier 2,000 | LARGE T&R
Inventory 10,000
Qty | Price (USD) 1ku | 4.559 1-99 8.389 100-249 6.839 250-999 5.375 1,000+ 4.559
Custom reel may be available