Packaging information
| Package | Pins SOIC (DW) | 24 |
| Operating temperature range (°C) -40 to 85 |
| Package qty | Carrier 2,000 | LARGE T&R |
Features for the SN74ABT8245
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test
Access Port
and Boundary-Scan Architecture - Functionally Equivalent to 'F245 and 'ABT245 in the Normal-Function Mode
- SCOPETM Instruction Set:
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel-Signature Analysis at Inputs With Masking Option
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Even-Parity Opcodes
- Two Boundary-Scan Cells per I/O for Greater Flexibility
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Package Options Include Plastic Small-Outline Packages (DW),
Ceramic Chip Carriers(FK), and Standard Ceramic DIPs (JT)
SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.
Description for the SN74ABT8245
The 'ABT8245 scan test devices with octal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F245 and 'ABT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers.
Data flow is controlled by the direction-control (DIR) and
output-enable (
) inputs. Data
transmission is allowed from the A bus to the B bus or from the B bus
to the A bus, depending on the logic level at DIR. The output-enable
() input can be
used to disable the device so that the buses are effectively
isolated.
In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8245 is characterized for operation from -40°C to 85°C.