Packaging information
| Package | Pins SOIC (DW) | 24 |
| Operating temperature range (°C) 0 to 70 |
| Package qty | Carrier 25 | TUBE |
Features for the SN74ALS869
- Fully Programmable With Synchronous Counting and Loading
- SN74ALS867A and ´AS867 Have Asynchronous Clear; SN74ALS869 and ´AS869 Have Synchronous Clear
- Fully Independent Clock Circuit Simplifies Use
- Ripple-Carry Output for n-Bit Cascading
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
Description for the SN74ALS869
These synchronous, presettable, 8-bit up/down counters feature
internal-carry look-ahead circuitry for cascading in high-speed
counting applications. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change
coincidentally with each other when so instructed by the count-enable
(
,
) inputs and internal gating. This
mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple-clock) counters. A buffered
clock (CLK) input triggers the eight flip-flops on the rising
(positive-going) edge of the clock waveform.
These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for
n-bit synchronous applications without additional gating. Two
count-enable (and ) inputs and a ripple-carry (
) output are instrumental in
accomplishing this function. Both and must be low to
count. The direction of the count is determined by the levels of the
select (S0, S1) inputs as shown in the function table. is fed forward to enable . thus enabled produces a low-level pulse while the count
is zero (all outputs low) counting down or 255 counting up (all
outputs high). This low-level overflow-carry pulse can be used to
enable successive cascaded stages. Transitions at and are allowed regardless of the level
of CLK. All inputs are diode clamped to minimize transmission-line
effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. With the
exception of the asynchronous clear on the SN74ALS867A and
´AS867, changes at S0 and S1 that modify the operating mode have
no effect on the Q outputs until clocking occurs. For the ´AS867
and ´AS869, any time ENP\ and/or ENT\ is taken high, either goes or remains high. For
the SN74ALS867A and SN74ALS869, any time is taken high, either goes or remains high. The
function of the counter (whether enabled, disabled, loading, or
counting) is dictated solely by the conditions meeting the stable
setup and hold times.
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C.