SN74AUP1G32DBVR ACTIVE

Features for the SN74AUP1G32

• Available in the ultra-small 0.64 mm² package (DPW) with 0.5-mm pitch
• Low static-power consumption
  (I_CC = 0.9 µA Max)
• Low dynamic-power consumption
  (C_pd = 4.3 pF Typ at 3.3 V)
• Low input capacitance (C_I = 1.5 pF Typ)
• Low noise – overshoot and undershoot
  <10% of V_CC
• I_off Supports live insertion, partial-power-down
  mode, and back drive protection
• Input hysteresis allows slow input transition and better switching noise immunity at the
  input (V_hys = 250 mV typ at 3.3 V)
• Wide operating V_CC range of 0.8 V to 3.6 V
• Optimized for 3.3-V operation
• 3.6-V I/O Tolerant to support mixed-mode signal operation
• t_pd = 4.6 ns Max at 3.3 V
• Suitable for point-to-point applications
• Latch-up performance exceeds 100 mA
  Per JESD 78, Class II
• ESD performance tested Per JESD 22
  • 2000-V Human-body model
    (A114-B, Class II)
  • 1000-V Charged-device model (C101)

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Description for the SN74AUP1G32

This single 2-input positive-OR gate performs the Boolean function in positive logic.