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Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Inventory: 53,986
Custom reel may be available

Download data sheet for SN74AUP1G80
  |   View additional information for SN74AUP1G80

Same as: SN74AUP1G80DCKRE4, SN74AUP1G80DCKRG4 

Packaging information

Package | Pins SOT-SC70 (DCK) | 5
Operating temperature range (℃) I (-40 to 85)
Package qty | Carrier: 3,000 | LARGE T&R
Custom reel may be available
View more packaging information

Quality information

RoHS Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-1-260C-UNLIM
Material content View
DPPM / MTBF / Fit rate View
Qualification summary View
Ongoing reliability monitoring View
Device marking View


  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model(C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications

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The AUP family is TI’s premier solution to the industry’s low-power needs inbattery-powered portable applications. This family assures a low static- and dynamic-powerconsumption across the entire VCC range of 0.8 V to 3.6 V, resulting inincreased battery life (see AUP – The Lowest-Power Family). This product also maintains excellentsignal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D)input meets the setup time requirement, the data is transferred to the Qoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage leveland is not directly related to the rise time of the clock pulse. Following the hold-time interval,data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs whenthe device is powered down. This inhibits current backflow into the device which prevents damage tothe device.

Qty Price
1-99 $0.14
100-249 $0.10
250-999 $0.08
1,000+ $0.05

Alternative carriers

Part number SN74AUP1G80DCKT
Package qty | Carrier 250 | SMALL T&R
Inventory 500
Qty | Price (USD) 1ku | $0.22