Packaging information
| Package | Pins SOT-23 (DBV) | 6 |
| Operating temperature range (°C) -40 to 125 |
| Package qty | Carrier 3,000 | LARGE T&R |
Features for the SN74AXCH1T45
- Fully Configurable Dual-Rail Design Allows Each Port to Operate With a Power Supply Range from 0.65 V to 3.6 V
- Operating Temperature: –40°C to +125°C
- Glitch-Free Power Supply Sequencing
- Bus-hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
- Maximum Quiescent Current (ICCA + ICCB) of 10 µA (85°C Maximum) and 16 µA (125°C Maximum)
- Up to 500-Mbps Support When Translating from 1.8 to 3.3 V
- VCC Isolation Feature
- If Either VCC Input is Below 100 mV, All I/Os Outputs are Disabled and Become High-Impedance
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 8000-V Human Body Model
- 1000-V Charged-Device Model
Description for the SN74AXCH1T45
The SN74AXCH1T45 is a single-bit noninverting bus transceiver that uses two individually configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6 V. Additionally the SN74AXCH1T45 is compatible with a single-supply system.
The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. If a supply is present for VCCA or VCCB, the bus-hold circuitry always remains active on the A or B inputs respectively, independent of the state of the direction control pin.
This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.
The VCC isolation feature ensures that if either VCCA or VCCB is less than 100 mV, both I/O ports enter a high-impedance state by disabling their outputs.
Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.