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SN74HC165DRG4 ACTIVE

8-Bit Parallel-Load Shift Registers

Inventory: 2,938
 
Custom reel may be available

Download data sheet for SN74HC165
  |   View additional information for SN74HC165

Same as: SN74HC165DRE4   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

Packaging information

Package | Pins SOIC (D) | 16
Operating temperature range (°C) Q (-40 to 125)
Package qty | Carrier: 2,500 | LARGE T&R
Custom reel may be available
View more packaging information

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-1-260C-UNLIM
Material content View
DPPM / MTBF / Fit rate View
Qualification summary View
Ongoing reliability monitoring View
Device marking View

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Maximum
  • Complementary Outputs
  • Direct Overriding Load (Data) Inputs
  • Gated Clock Inputs
  • Parallel-to-Serial Data Conversion
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise
    Noted. On All Other Products, Production
    Processing Does Not Necessarily Include Testing
    of All Parameters.

Description

The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

Qty Price
1-99 $0.290
100-249 $0.197
250-999 $0.152
1,000+ $0.101