The device contains two independent D-type positive-edge-triggered flip-flops. All inputsinclude Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset(PRE) input sets the output high. A low level at the clear(CLR) input resets the output low. Preset and clear functions areasynchronous and not dependent on the levels of the other inputs. When PREand CLR are inactive (high), data at the data (D) input meeting the setuptime requirements is transferred to the outputs (Q, Q) on the positive-goingedge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directlyrelated to the rise time of the input clock (CLK) signal. Following the hold-time interval, data atthe data (D) input can be changed without affecting the levels at the outputs (Q,Q).