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SN74LS166AD ACTIVE

Serial-out shift registers

Inventory: 995  
 

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-1-260C-UNLIM
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (℃)
SOIC (D) | 16 40 | TUBE
0 to 70
Package | Pins SOIC (D) | 16
Package qty | Carrier: 40 | TUBE
Operating temperature range (℃) 0 to 70
View TI packaging information

Features for the SN74LS166A

  • Synchronous Load
  • Direct Overriding Clear
  • Parallel to Serial Conversion

 

Description for the SN74LS166A

The '166 and 'LS166A 8-bit shift registers are compatible with most other TTL logic families. All '166 and 'LS166A inputs are buffered to lower the drive requirements to one Series 54/74 or Series 54LS/74LS standard load, respectively. Input clamping diodes minimize switching transients and simplify system design.

These parallel-in or serial-in, serial-out shift registers have a complexity of 77 equivalent gates on a monolithic chip. They feature gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This, of course, allows the system clock to be free-running and the register can be stopped on command with the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.

 

Pricing


Qty Price (USD)
1-99 0.902
100-249 0.694
250-999 0.511
1,000+ 0.365

Additional package qty | carrier options

Package qty | Carrier 2,500 | LARGE T&R
Inventory Out of Stock
Qty | Price (USD) 1ku | 0.304 1-99 0.751 100-249 0.578 250-999 0.425 1,000+ 0.304
Custom reel may be available