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SN74LV165ADR ACTIVE

Parallel-Load 8-Bit Shift Registers

US ECCN: EAR99 US/Local Export Classification Number

NEW - Custom reel may be available
Inventory: 39,351  
 

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU, SN
MSL rating / Peak reflow Level-1-260C-UNLIM
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (°C)
SOIC (D) | 16 2,500 | LARGE T&R
Custom reel may be available
-40 to 125
Package | Pins SOIC (D) | 16
Package qty | Carrier: 2,500 | LARGE T&R
Custom reel may be available
Operating temperature range (°C) -40 to 125
View TI packaging information

Features for the SN74LV165A

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 10.5 ns at 5 V
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Description for the SN74LV165A

The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.

When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output, QH.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Pricing


Qty Price (USD)
1-99 0.301
100-249 0.205
250-999 0.158
1,000+ 0.105

Additional package qty | carrier options

Package qty | Carrier 40 | TUBE
Inventory 3,227
Qty | Price (USD) 1ku | 0.126 1-99 0.362 100-249 0.246 250-999 0.19 1,000+ 0.126