This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-VVCC operation.
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A low level at the preset (PRE) or clear(CLR) input sets or resets the outputs, regardless of the levels of theother inputs. When PRE and CLR are inactive (high),data at the data (D) input meeting the setup time requirements is transferred to the outputs on thepositive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is notrelated directly to the rise time of the clock pulse. Following the hold-time interval, data at theD input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.