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SN74LVC2G74DCURG4 ACTIVE

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Same as: SN74LVC2G74DCURE4   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

NEW - Custom reel may be available
Inventory: 2,750  
 

Quality information

RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-1-260C-UNLIM
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
View or download

Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (℃)
VSSOP (DCU) | 8 3,000 | LARGE T&R
Custom reel may be available
-40 to 125
Package | Pins VSSOP (DCU) | 8
Package qty | Carrier: 3,000 | LARGE T&R
Custom reel may be available
Operating temperature range (℃) -40 to 125
View TI packaging information

Features for the SN74LVC2G74

  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.9 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model

Description for the SN74LVC2G74

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Pricing


Qty Price (USD)
1-99 0.402
100-249 0.273
250-999 0.211
1,000+ 0.14

Additional package qty | carrier options

Package qty | Carrier 250 | SMALL T&R
Inventory 48,450
Qty | Price (USD) 1ku | 0.272 1-99 0.672 100-249 0.517 250-999 0.381 1,000+ 0.272