The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The information obtained includes the type and condition of the operation performed and any error conditions encountered.
The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can significantly reduce software overhead and increase system efficiency by automatically controlling serial-data flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor between 1 and 216 1.
The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.