|Package | Pins||FCBGA (CTR) | 144|
|Operating temperature range (℃)||I (-40 to 85)|
|Package qty | Carrier:||
119 | JEDEC TRAY (5+1)
- Automatic Digital Multiplexing/De-Multiplexing of 1 to 8
Independent Lower Speed Gigabit Serial Lines into a Single
Higher Speed Gigabit Serial Line with Extensive Media
- 1∼8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing
- 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
- Dynamic Port Aggregation Supported
- Programmable High Speed Redundant Switching
- Wide Data Rate Range for Multiple Application Support
- Transmit De-Emphasis and Adaptive Receiver Equalization on
Both Low Speed and High Speed Sides
- MDIO Clause 22 control interface
- 8B/10B ENDEC Coding Support
- Raw (Unencoded) Data Support
- Core Supply 1V; I/O: 1.5V/1.8V
- Superior Signal Integrity Performance
- Low Power Operation: < 800 mW per channel (typ)
- Rate Matching Support (For compatible data protocols like GE PCS)
- Full Non-Blocking Receiver Crosspoint Mapping Capability
- Flexible Clocking
- Multi Drive Capability (SFP+, backplane, cable)
- Support for Programmable High Speed Lane Alignment Characters
- Support for Programmable HS/LS 10-Bit Alignment Characters
- Wide Range of Built-in Test Patterns
- 144-pin, 13mmx13mm FCBGA Package
The TLK10081 is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.
The TLK10081 has a low-speed interface which can accommodate one to eight bidirectional serial links running at rates from 250 Mbps to 1.25 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces can operate at rates from 1 Gbps to 10 Gbps. The high speed interface is designed to run at 8 x the low speed serial rate regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.
A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so TX may operate in 8:1 mode while RX operates in 1:1 mode. This independence is restricted to using the same low speed line rate. For example, the TX can operate at 8 × 1.25 Gbps while RX operates at 1 × 1.25 Gbps.
The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.
The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.
The TLK10081 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.
Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.
To aid in system synchronization, the TLK10081 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.
The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.