Packaging information
| Package | Pins VQFN (RGP) | 20 |
| Operating temperature range (°C) -40 to 100 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the TLK1101E
- Multi-Rate Operation up to 11.3Gbps
- Compensates for up to 30dB Loss on the Receive Side and up to 7dB Loss on the Transmit Side at 5.65GHz
- Input Offset Cancellation
- Output Disable/Squelch Function
- Loss Of Signal Detection
- Adjustable Output Swing
- Adjustable Output De-Emphasis
- Two-Wire Serial Interface
- Single 3.3V Supply
- Surface Mount Small Footprint 4-mm × 4-mm 20-Pin QFN Package
- APPLICATIONS
- High-Speed Links In Communication And Data Systems
- SFP+ and XFP Active Cables
- Backplane, Daughtercard, and Cable Interconnects for 10GE, 8GFC, 10GFC, 10G SONET, SAS, SATA
Description for the TLK1101E
The TLK1101E is a versatile and flexible high-speed equalizer for applications in digital high-speed links with data rates up to 11.3Gbps.
The TLK1101E can be configured in many ways to optimize its performance. It provides output de-emphasis adjustable from 0dB to 7dB using pins DE0 and DE1.
The output differential voltage swing can be set to 300mVp-p, 600mVp-p, or 900mVp-p using the SWG pin. A controlling voltage on pin VTH can be used to adjust the input threshold voltage.
Pins LN0 and LN1 can be used to optimize the device performance for various interconnect lengths, e.g. from 0 to 20 meters of 24-AWG twinaxial cable.
The LOS (loss of signal) assert level can be set to a desired level through a controlling voltage connected to pin LOSL. The LOS assert levels can be chosen from two LOS assert level ranges selectable with the LOSR pin.
The output can be disabled using the DIS pin. The DIS and the LOS pin can be connected together to implement a squelch function.
The de-emphasis, the output voltage swing, the input threshold voltage, the output disable, and the LOS assert levels and ranges can alternatively be set using the two-wire serial interface through the SCL and SDA pins. The external pin configuration is the default device setup method. The active device control method is selected through register address 0 bit 0 (see Table 4 and Table 20). The two-wire serial interface also allows for the control of the input bandwidth to optimize the device performance for various data rates.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1600mVp-p differential.
The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA out-of-band (OOB) signals.