|Package | PIN:||SOT-23 (DBV) | 5|
|Temp:||Q (-40 to 125)|
- Wide operating voltage: 1.5 V to 10 V
- Nano supply current: 300 nA (Typ), 700 nA (Max)
- Fixed threshold voltage (VIT-)
- Threshold from 1.6 V to 4.9 V in 0.1-V steps
- Highaccuracy: 1% (Typ), 1.5% (Max)
- Built-in hysteresis(VIT+)
- 1.6 V < VIT- ≤ 3.0 V = 100 mV (Typical)
- 3.1 V ≤ VIT- < 4.9 V = 200 mV (Typical)
- Start-up delay (tSTRT): 220 µs (Typ), 350 µs (Max)
- Programmable reset time delay (tD):
- 50 µs (no capacitor) to6.2 s (10-µF)
- Active-low manual reset (MR)
- Three output topologies:
- TPS3840DL: open-drain, active-low (RESET), requirespull-up resistor
- TPS3840PL: push-pull, active-low(RESET)
- TPS3840PH: push-pull, active-high (RESET)
- Wide temperature range: –40°C to +125°C
- Package: SOT23-5 (DBV)
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Texas Instruments TPS3840DL42DBVR
Wide Vin allows monitoring 9V rails or batteries without external components and 24Vrails with external resistors. Nano-Iq extends battery life for low power applications andminimizes current consumption when using external resistors. Fast start-up delay allows thedetection of a voltage fault before the rest of the system powers up providing maximum safety inhazardous start-up fault conditions. Low Power-on-Reset (VPOR) preventsfalse resets, premature enable or turn-on of next device, and proper transistor control duringpower-up and power-down.
Reset output signal is asserted when the voltage at VDD dropsbelow the negative voltage threshold (VIT-) or when manual reset(MR) is pulled to a low logic(VMR_L). Reset signal is cleared whenVDD rise above VIT- plus hysteresis(VIT+) and manual reset is floating or aboveVMR_H and the reset time delay(tD) expires. Reset time delay can be programmed by connecting a capacitorbetween CT pin and ground. For a fast reset CT pin can be left floating.
Additional features: Built-in glitch immunity protection for MRand VDD, built-in hysteresis, low open-drain output leakage current(ILKG(OD)).