Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps
Features for the TSW14J57EVM
- Quickly evaluate JESD204B and JESD204C ADC, DAC or AFE performance using TI HSDC Pro software
- Direct connection to all TI JESD204B and JESD204C EVMs using an FMC+ standard connector (backwards compatible to FMC-equipped EVMs)
- JESD204B and JESD204C RX and TX IP cores with 16 routed transceiver channels; operating range from 1.6 Gbps to 15 Gbps
- Support for SUBCLASS 0 and 1 operation
- Onboard high-speed USB 3.0-to-parallel converter bridges the FPGA interface to the host PC and GUI
- 16-Gb DDR4 SDRAM (split into four independent 256 × 16, 4-Gb SDRAMs; total of 1G 16-bit samples)
Description for the TSW14J57EVM
The TI TSW14J57 evaluation module (EVM) is a next-generation data capture card used to evaluate the performance of the new TI JESD204B family of high-speed analog-to-digital converters (ADCs), high-speed digital-to-analog converters (DACs) and analog front ends (AFEs).
Populated with an Arria® 10 device and using the Altera® JESD204B IP solution, the TSW14J57 can be dynamically configured to support all lane speeds from 1.6 Gbps to 15 Gbps - from 1 to 16 lanes.
Together with the accompanying High-Speed Data Converter Pro (HSDC Pro) graphic user interface (GUI), it is a complete system that captures and evaluates data samples from ADC, DAC and AFE EVMs that use JESD204B and/or JESD204C.