Packaging information
| Package | Pins SOT-23 (DBV) | 5 |
| Operating temperature range (°C) -40 to 140 |
| Package qty | Carrier 250 | SMALL T&R |
Features for the UCC27537
- Low-cost gate driver (offering optimal solution for driving FET and IGBTs)
- Superior replacement to discrete transistor pair drive (providing easy interface with controller)
- TTL and CMOS compatible input logic threshold (independent of supply voltage)
- Split output options allow for tuning of turnon and turnoff currents
- Inverting and noninverting input configurations
- Enable with fixed TTL compatible threshold
- High 2.5-A source and 2.5-A or 5-A sink peak drive currents at 18-V VDD
- Wide VDD range from 10 V to 35 V
- Input and enable pins capable of with standing up to –5-V DC below ground
- Output held low when inputs are floating or during VDD UVLO
- Fast propagation delays (17-ns Typical)
- Fast rise and fall times
(15-ns and 7-ns typical with 1800-pF Load) - Undervoltage lockout (UVLO)
- Used as a high-side or low-side driver (if designed with proper bias and signal isolation)
- Low-cost, space-saving 5-pin or 6-pin DBV (SOT-23) package options
- UCC27536 and UCC27537 pin-to-pin compatible to TPS2828 and TPS2829
- Operating temperature range of –40°C to 140°C
Description for the UCC27537
The UCC2753x single-channel, high-speed gate drivers can effectively drive MOSFET and IGBT power switches. Using a design that allows for a source of up to 2.5 A and 5-A sink through asymmetrical drive (split outputs), coupled with the ability to support a negative turn-off bias, rail-to-rail drive capability, extremely small propagation delay (17 ns typical), the UCC2753x devices are ideal solutions for MOSFET and IGBT power switches. The UCC2753x family of devices can also support enable, dual input, and inverting and non-inverting input functionality. The split outputs and strong asymmetrical drive boost the devices immunity against parasitic Miller turn-on effect and can help reduce ground debouncing.
Leaving the input pin open holds the driver output low. The logic behavior of the driver is shown in the application diagram, timing diagram, and input and output logic truth table.
Internal circuitry on VDD pin provides an undervoltage lockout function that holds output low until VDD supply voltage is within operating range.