XDRA829JXXGALF ACTIVE

Features for the DRA829J

Processor cores:

• Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
  • 1MB shared L2 cache per dual-core Arm Cortex-A72 cluster
  • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 Core
• Six Arm Cortex-R5F MCUs at up to 1.0 GHz, 8K DMIPS
  • 16K I-Cache, 16K D-Cache, 64K L2 TCM
  • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
  • Four Arm Cortex-R5F MCUs in general compute partition
• Deep-learning Matrix Multiply Accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
• C7x floating point, vector DSP, up to 1.0 GHz, 80 GFLOPS, 256 GOPS
• Two C66x floating point DSP, up to 1.35 GHz, 40 GFLOPS, 160 GOPS
• 3D GPU PowerVR Rogue 8XE GE8430, up to 750 MHz, 96 GFLOPS, 6 Gpix/sec

  Memory subsystem:

• 2MB of on-chip L3 RAM with ECC and coherency
  • ECC error protection
  • Shared coherent cache
  • Supports internal DMA engine
• External Memory Interface (EMIF) module with ECC
  • Supports LPDDR4 memory types
  • Supports speeds up to 4266 MT/s
  • 32-bit data bus with inline ECC up to 14.9GB/s
• General-Purpose Memory Controller (GPMC)
• 512KB on-chip SRAM in MAIN domain, protected by ECC

  Display subsystem:

• One eDP/DP interface with Multi-Display Support (MST)
  • HDCP1.4/HDCP2.2 high-bandwidth digital content protection
• One DSI TX (up to 2.5K)
• Up to two DPI

  Video acceleration:

• Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
• Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
• Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode

  Functional Safety:

• Functional Safety-Compliant targeted
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
  • Systematic capability up to ASIL-D/SIL-3 targeted
  • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
  • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
  • Safety-related certification
    • ISO 26262 planned

• Device security:

• Secure boot with secure runtime support
• Customer programmable root key, up to RSA-4K or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

  High speed serial interfaces:

• Two CSI2.0 4L RX plus one CSI2.0 4L TX
• Integrated ethernet switch supporting (total of 8 external ports)
  • Up to eight 2.5Gb SGMII
  • Up to eight RMII (10/100) or RGMII (10/100/1000)
  • Up to two QSGMII
• Up to four PCI-Express (PCIe) Gen3 controllers
  • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Up to two lanes per controller
• Two USB 3.0 dual-role device (DRD) subsystem
  • Two enhanced SuperSpeed Gen1 ports
  • Each port supports Type-C switching
  • Each port independently configurable as USB host, USB peripheral, or USB DRD

  Automotive interfaces:

• Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support

  Audio interfaces:

• Twelve Multichannel Audio Serial Port (MCASP) modules

  Flash memory interfaces:

• Embedded MultiMediaCard interface ( eMMC™ 5.1)
• Universal Flash Storage (UFS 2.1) interface with two lanes
• Two Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
• Two simultaneous flash interfaces configured as
  • One OSPI and one QSPI flash interfaces
  • or HyperBus™ and QSPI flash interface

  System-on-Chip (SoC) architecture:

• 16-nm FinFET technology
• 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing

  TPS6594-Q1 Companion Power Management ICs (PMIC):

• Functional Safety support up to ASIL-D
• Flexible mapping to support different use cases

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Description for the DRA829J

Jacinto™ 7 DRA829 processors, based on the Arm®v8 64-bit architecture, provide advanced system integration to enable lower system costs of automotive and industrial applications. The integrated diagnostics and functional safety features are targeted to ASIL-B/C or SIL-2 certification/requirements. The integrated microcontroller (MCU) island eliminates the need for an external system MCU. The device features a Gigabit Ethernet switch and a PCIe hub which enables networking use cases that require heavy data bandwidth. Up to four Arm Cortex-R5F subsystems manage low level, timing critical processing tasks leaving the Arm Cortex-A72’s unencumbered for applications. A dual-core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor.