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74SSTVF32852ZKFR

24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs

Packaging

Package | PIN: ZKF | 114
Temp: C (0 to 70)
Carrier: Cut Tape
Qty Price
1-9 $14.63
10-24 $13.60
25-99 $13.13
100-249 $11.47
250-499 $10.91
500-749 $10.04
750-999 $9.02
1000+ $8.99

Features

  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
  • Pinout and Functionality Compatible With JEDEC Standard SSTV32852
  • Pinout Optimizes 1U DDR DIMM Layout
  • 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV32852 in PC2700 DIMM Applications
  • 1-to-2 Outputs Support Stacked DDR DIMMs
  • One Device Per DIMM Required
  • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

Texas Instruments  74SSTVF32852ZKFR

This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications.

The SN74SSTVF32852 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.