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ADS54J20IRMP

Dual-Channel, 12-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)

Packaging

Package | PIN: RMP | 72
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $430.16
10-24 $406.26
25-99 $396.02
100+ $387.95

Features

  • 12-Bit Resolution, Dual-Channel, 1-GSPS ADC
  • Noise Floor: –157 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 67.8 dBFS
    • NSD: –155 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 65.6 dBFS
    • NSD: –152.6 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 10.0 Gbps
    • 4 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-Pin VQFNP (10 mm × 10 mm)

Texas Instruments  ADS54J20IRMP

The ADS54J20 is a low-power, wide-bandwidth, 12-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Optionally, each ADC channel can be connected to a wideband digital down-converter (DDC) block. The ADS54J20 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 12-bit data from each channel.