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Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling Analog-to-Digital Converter (ADC)


Package | PIN: RMP | 72
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $661.90
10-24 $625.13
25-99 $609.37
100+ $596.95


  • Quad Channel, 14-Bit Resolution
  • Maximum Sampling Rate: 1 GSPS
  • Maximum Output Sample Rate: 500 MSPS
  • High-Impedance Analog Input Buffer
  • Analog Input Bandwidth (–3 dB): 1 GHz
  • Output Options:
    • Digital Down Conversion (DDC) Using 16-Bit NCO
    • DDC Bypass With Full Rate Output Up to500 MSPS
  • Differential Full-Scale Input: 1.1 VPP
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • Spectral Performance:
    • fIN = 190-MHz IF at –1dBFS:
      • SNR: 69 dBFS
      • NSD: –153 dBFS/Hz
      • SFDR: 86 dBc (HD2, HD3),
        95 dBFS (Non HD2, HD3)
    • fIN =370-MHz IF at –3 dBFS:
      • SNR: 68.5 dBFS
      • NSD: –152.5 dBFS/Hz
      • SFDR: 80 dBc (HD2, HD3),
        86 dBFS (Non HD2, HD3)
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Power Consumption: 625 mW/Ch, 2.5 W Total
  • Power Supplies: 1.15 V, 1.15 V, 1.9 V

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Texas Instruments  ADS54J64IRMP

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and highSNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one laneper channel. The buffered analog input provides uniform impedance across a wide frequency range andminimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamicrange (SFDR) over a large input frequency range with very low power consumption. The digital signalprocessing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPSoutput in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integrationdensity. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derivethe bit clock that is used to serialize the 14-bit data from each channel.