ADS54J66IRMP

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ADS54J66IRMP

Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

Packaging

Package | PIN: RMP | 72
Temp: I (-40 to 85)
Carrier: Partial Tray
Qty Price
1-9 $595.37
10-24 $562.29
25-99 $548.12
100+ $536.95

Features

  • Quad Channel
  • 14-Bit Resolution
  • Maximum Clock Rate: 500 MSPS
  • Input Bandwidth (3 dB): 900 MHz
  • On-Chip Dither
  • Analog Input Buffer with High-Impedance Input
  • Output Options:
    • Rx: Decimate-by-2 and -4 Options with
      Low-Pass Filter
    • 200-MHz Complex Bandwidth or 100-MHz
      Real Bandwidth Support
    • DPD FB: 500 MSPS
  • 1.9-VPP Differential Full-Scale Input
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Key Specifications:
    • Power Dissipation: 675 mW/ch
    • Spectral Performance (Un-Decimated)
      • fIN = 190 MHz IF at –1 dBFS:
        • SNR: 69.5 dBFS
        • NSD: -153.5 dBFS/Hz
        • SFDR: 86 dBc (HD2, HD3),
          93 dBFS (non HD2, HD3)
      • fIN = 370 MHz IF at –3 dBFS:
        • SNR: 68.5 dBFS
        • NSD: –152.5 dBFS/Hz
        • SFDR: 81 dBc (HD2, HD3),
          86 dBFS (Non HD2, HD3)

Texas Instruments  ADS54J66IRMP

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop (PLL) multiplies the incoming analog-to-digital converter (ADC) sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.