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CD4001UBE

CMOS Quad 2-Input NOR Gate

Packaging

Package | PIN: N | 14
Temp: M (-55 to 125)
Carrier: Partial Tube
Qty Price
1-9 $0.42
10-24 $0.37
25-99 $0.34
100-249 $0.29
250-499 $0.26
500-749 $0.20
750-999 $0.15
1000+ $0.13

Features

  • Propagation delay time = 30 ns (typ.) at CL = 50 pF, VDD = 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for maximum quiescent current at 20 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings

Data sheet acquired from Harris Semiconductor

Texas Instruments  CD4001UBE

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates.

The CD4001UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).