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CMOS dual complementary pair plus inverter


Package | PIN: N | 14
Temp: M (-55 to 125)
Carrier: Partial Tube
Qty Price
1-9 $0.42
10-24 $0.37
25-99 $0.34
100-249 $0.29
250-499 $0.26
500-749 $0.20
750-999 $0.15
1000+ $0.13


  • Standardized symmetrical output characteristics
  • Medium Speed Operation — tPHL, tPLH = 30 ns (typ.) at 10 V
  • 100% tested for quiescent current at 20 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Applications:
    • Extremely high-input impedance amplifiers
    • Shapers
    • Inverters
    • Threshold detector
    • Linear amplifiers
    • Crystal oscillators

Data sheet acquired from Harris Semiconductor

Texas Instruments  CD4007UBE

CD4007UB types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Fig. 2.

More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed.

The CD4007UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).