CD4019BPWR

text.skipToContent text.skipToNavigation

CD4019BPWR

CMOS Quad AND/OR Select Gate

Packaging

Package | PIN: PW | 16
Temp: M (-55 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.35
10-24 $0.31
25-99 $0.28
100-249 $0.24
250-499 $0.22
500-749 $0.17
750-999 $0.13
1000+ $0.11

Features

  • Medium speed operation……tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Applications:
    • AND-OR select gating
    • Shift-right/shift-left registers
    • True/complement selection
    • AND/OR/Exclusive-OR selection

Texas Instruments  CD4019BPWR

CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.

The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).