CD4516BPWR

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CD4516BPWR

CMOS Presettable Binary Up/Down Counter

Packaging

Package | PIN: PW | 16
Temp: M (-55 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.39
10-24 $0.34
25-99 $0.31
100-249 $0.27
250-499 $0.24
500-749 $0.19
750-999 $0.14
1000+ $0.12

Features

  • Medium-speed operation - fCL = 8 NHz typ. at 10 V
  • Synchronous internal carry propagation
  • Reset and Preset capability
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized, symmetrical output characteristics
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Up/Down difference counting
    • Multistage synchronous counting
    • Multistage ripple counting
    • Synchronous frequency dividers

CD4510B ---BCD Type
CD4516B ---Binary Type

Texas Instruments  CD4516BPWR

CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode.

If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage.

The CD4510B and CD4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. (See Fig.15).

These devices are similar to types MC14510 and MC14516.

The CD4510B and CD4516B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4516B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).