|Package | PIN:||D | 16|
|Temp:||M (-55 to 125)|
- Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption
- Digital Design Avoids Analog Compensation Errors
- Easily Cascadable for Higher-Order Loops
- Useful Frequency Range
- DC to 110 MHz Typical (K CLK)
- DC to 70 MHz Typical (I/D CLK)
- Dynamically Variable Bandwidth
- Very Narrow Bandwidth Attainable
- Power-On Reset
- Output Capability
- Standard: XORPD OUT, ECPD OUT
- Bus Driver: I/D OUT
- SCR Latch-Up-Resistant CMOS Process and Circuit Design
- Balanced Propagation Delays
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Texas Instruments CD74ACT297M
The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. This device contains all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked loops as shown in Figure 1.
Both exclusive-OR phase detectors (XORPDs) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher-order phase-locked loops.
The length of the up/down K counter is digitally programmable according to the K-counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth, or capture range, and shortens the lock time of the loop. When A, B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth, or capture range, and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs can maximize the overall performance of the digital phase-locked loop.
This device performs the classic first-order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock (K CLK), increment/decrement clock (I/D CLK), and loop propagation delays. The I/D clock frequency and the divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D clock/2N (Hz).