CD74HC112M96

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CD74HC112M96

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Packaging

Package | PIN: D | 16
Temp: M (-55 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.59
10-24 $0.52
25-99 $0.47
100-249 $0.40
250-499 $0.37
500-749 $0.28
750-999 $0.22
1000+ $0.19

Features

  • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
  • Asynchronous Set and Reset
  • Complementary Outputs
  • Buffered Inputs
  • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

Texas Instruments  CD74HC112M96

The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Set, Reset, and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs.

The HCT logic family is functionally as well as pin-compatible with the standard LS logic family.