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High Speed CMOS Logic Dual Decade Ripple Counters


Package | PIN: D | 16
Temp: M (-55 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.61
10-24 $0.54
25-99 $0.49
100-249 $0.42
250-499 $0.38
500-749 $0.29
750-999 $0.22
1000+ $0.19


  • Two BCD Decade or Bi-Quinary Counters
  • One Package Can Be Configured to Divide-by-2, 4, 5,10, 20, 25, 50 or 100
  • Two Master Reset Inputs to Clear Each Decade Counter Individually
  • Fanout (Over Temperature Range)
    - Standard Outputs...10 LSTTL Loads
    - Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    - 2V to 6V Operation
    - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    - 4.5V to 5.5V Operation
    - Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    - CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

Texas Instruments  CD74HC390M96

The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0\ and nCP1\) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCP0\ and nCP1\).

For BCD decade operation, the nQ0 output is connected to the nCP1\ input of the divide-by-5 section. For bi-quinary decade operation, the nO3 output is connected to the nCP0\ input and nQ0 becomes the decade output.

The master reset inputs (1MR and 2MR) are active-High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the "1" and "2" prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low.