CD74HC75PWR

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CD74HC75PWR

High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latches

Packaging

Package | PIN: PW | 16
Temp: M (-55 to 125)
Carrier: Cut Tape
Qty Price
1-9 $0.63
10-24 $0.56
25-99 $0.52
100-249 $0.44
250-499 $0.41
500-749 $0.33
750-999 $0.27
1000+ $0.24

Features

  • True and Complementary Outputs
  • Buffered Inputs and Outputs
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

Texas Instruments  CD74HC75PWR

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.