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CDCI6214RGET

PCIe Gen4 Support Ultra-Low Power Clock Generator With Four Programmable Outputs and EEPROM

Packaging

Package | PIN: RGE | 24
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $5.54
10-24 $4.98
25-99 $4.66
100-249 $4.18
250-499 $3.90
500-749 $3.39
750-999 $2.94
1000+ $2.88

Features

  • One Configurable High Performance, Low-Power PLL With 4 Programmable Outputs
  • RMS Jitter Performance
    • Supports PCIe Gen1 with or without Spread Spectrum Clocking (SSC)
    • Supports PCIe Gen2 / Gen3 / Gen4 without SSC
  • Typical Power Consumption: 150 mW at 1.8 V(2)
  • Universal Clock Input
    • Differential AC-Coupled or LVCMOS:1 MHz to 250 MHz
    • Crystal: 8 MHz to 50 MHz
  • Flexible Output Frequencies
    • 44.1 kHz to 350 MHz
    • Glitch-Less Output DividerSwitching
  • Four Individually Configurable Outputs
    • LVCMOS, LVDS or HCSL
    • Differential AC-CoupledWith Programmable Swing (LVDS-, CML-, LVPECL-Compatible)
  • Fully Integrated PLL, Configurable Loop Bandwidth: 100 kHz to 3 MHz
  • Single or Mixed Supply Operation for Level Translation: 1.8 V, 2.5 V and 3.3 V
  • Configurable GPIOs
    • Status Signals
    • Up to 4 Individual Output Enables
    • Output Divider Synchronization
  • Flexible Configuration Options
    • I2C-Compatible Interface: Up to 400kHz
    • Integrated EEPROM With Two Pages and External Select Pin
  • Only Supports 100 Ω Systems
  • Industrial Temperature Range: –40ºC to 85ºC
  • Small Footprint: 24-Pin VQFN (4 mm × 4 mm)

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Texas Instruments  CDCI6214RGET

The CDCI6214device is an ultra-low power clock generator. The device selects between two independent referenceinputs to a phase-locked loop and generates up to four different frequencies on configurabledifferential output channels and also a copy of the reference clock on a LVCMOS outputchannel.

Each of the four output channels has a configurable integer / fractional outputdivider and a dedicated integer divider. Together with the output muxes, this allows up tofive different frequencies. Clock distribution dividers are reset in a deterministic way for cleanclock gating and glitch-less update capability. Flexible power-down options allow to optimize thedevice for lowest power consumption in active and standby operation. Typically four 156.25 MHz LVDSoutputs consume 150 mW at 1.8V. Typical RMS jitter of 386 fs for 100 MHz HCSL output enhancessystem margin for PCIe applications.

The CDCI6214 isconfigured using internal registers that are accessed by anI2C-compatible serial interface and internal EEPROM.

The CDCI6214enables high-performance clock trees from a single reference at ultra-low power with a smallfootprint. The factory- and user-programmable EEPROM make the CDCI6214 ideal as easy-to-use, instant-on clocking solution with low powerconsumption.