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Ultra Low Power, 2:8 Fan-out Buffer with Universal Inputs and Outputs


Package | PIN: RHB | 32
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $8.14
10-24 $7.57
25-99 $7.30
100-249 $6.38
250-499 $6.07
500-749 $5.59
750-999 $5.02
1000+ $5.00


  • Support PCIE gen1, gen2, gen3
  • Configuration Options (via pins or SPI/I2C):
    • Input Type (HCSL, LVDS, LVCMOS)
    • Output Type (HCSL, LVDS, LVCMOS)
    • Signal Edge Rate (Slow, Medium, Fast)
    • Clock Input Divide Value (/1, /2, /4, /8) – IN2 Only
  • Low Power Consumption and Power Management Features Including 1.8V Operation and Output Enable Control
  • Integrated Voltage Regulators Improve PSNR
  • Excellent Additive Jitter Performance
    • 200 fs RMS (10 kHz to 20 MHz), LVDS at
      100 MHz
    • 160 fs RMS (10 kHz to 20 MHz), HCSL at
      100 MHz
  • Maximum Operating Frequency:
    • Differential Mode: up to 400 MHz
    • LVCMOS Mode: up to 250 MHz
  • ESD Protection Exceeds 2 kV HBM, 500 V CDM
  • Industrial Temperature Range (–40°C to 85°C)
  • Wide Supply Range (1.8 V, 2.5 V, or 3.3 V)

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Texas Instruments  CDCUN1208LPRHBR

The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, twouniversal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edgerate control. The clock buffer supports PCIE gen1, gen2 and gen3. One of the device inputs includesa divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32 pinQFN package reducing the solution footprint. The device is flexible and easy to use. The state ofcertain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides aSPI/I2C port with which a host processor controls device settings. TheCDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The outputsection includes four dedicated supply pins enabling the operation of output ports from differentpower supply domains. This provides the ability to clock devices switching at different LVCMOSlevels without the need for external logic level translation circuitry.