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CY74FCT573ATSOCT

Octal Transparent D-Type Latches with 3-State Outputs

Packaging

Package | PIN: DW | 20
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $0.68
10-24 $0.61
25-99 $0.56
100-249 $0.48
250-499 $0.45
500-749 $0.36
750-999 $0.29
1000+ $0.26

Features

  • Function and Pinout Compatible With FCT and F Logic
  • Reduced VOH(Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • 3-State Outputs
  • CY54FCT573T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT573T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

Texas Instruments  CY74FCT573ATSOCT

The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.