|Package | PIN:||PFB | 48|
|Temp:||I (-40 to 85)|
- Digital Audio Interface Transmitter (DIT)
- Supports Sampling Rates Up to 216 kHz
- Includes Differential Line Driver and CMOS-Buffered Outputs
- Digital Audio Interface Receiver (DIR)
- PLL Lock Range Includes Sampling Rates from 20 kHz to 216 kHz
- Four Differential-Input Line Receivers and an Input Multiplexer
- Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs
- Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)
- Audio CD Q-Channel Sub-Code Decoding and Data Buffer
- Low Jitter Recovered Clock Output
- User-Selectable Serial Host Interface: SPI™ or I2C
- Provides Access to On-Chip Registers and Data Buffers
- Status Registers and Interrupt Generation for Flag and Error Conditions
- Block-Sized Data Buffers for Both Channel Status and User Data
- Two Audio Serial Ports (Ports A and B)
- Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic
- Slave or Master Mode Operation With Sampling Rates Up to 216 kHz
- Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats
- Supports Audio Data Word Lengths Up to 24 Bits
- Four General-Purpose Digital Outputs
- Multifunction Programmable Through Control Registers
- Extensive Power-Down Support
- Functional Blocks May Be Disabled Individually When Not In Use
- Operates From 1.8-V Core and 3.3-V I/O Power Supplies
- Small TQFP-48 Package, Compatible With the SRC4382 and SRC4392
Texas Instruments DIX4192IPFBR
The DIX4192 device is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.
The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR lock range includes sampling rates from 20 kHz to 216 kHz.
The DIX4192 device is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options through control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.
The DIX4192 device requires a 1.8-V core logic supply, in addition to a 3.3-V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from 1.65 V to 3.6 V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The DIX4192 device is available in a lead-free, TQFP-48 package, and is pin- and register-compatible with the Texas Instruments SRC4382 and SRC4392 products.