|Package | PIN:||PFB | 48|
|Temp:||I (-40 to 85)|
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade:
- DIX4192I-Q1: Grade 3 (–40°C to +85°C)
- DIX4192T-Q1: Grade 2 (–40°C to +105°C)
- Device HBM ESD ClassificationLevel 2
- Device CDM ESD Classification Level C4B
- Device Temperature Grade:
- Digital Audio Interface Transmitter (DIT)
- PCM/Encoded data to S/PDIFConversion
- Supports Sampling Rates Up to 216 kHz
- Includes Differential Line Driver and
- Digital Audio Interface Receiver (DIR)
- S/PDIF to Stereo PCM Conversion / Encodeddata
- PLL Lock Range Includes Sampling Rates from 20 kHz to 216 kHz
- Four Differential-Input Line Receivers and an Input Multiplexer
- Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and BufferOutputs
- Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937formats)
- Audio CD Q-Channel Sub-Code Decoding and Data Buffer
- Low Jitter Recovered Clock Output
- User-Selectable Serial Host Interface: SPI™ or I2C
- Provides Access to On-Chip Registers and DataBuffers
- Status Registers and Interrupt Generation for Flag and ErrorConditions
- Block-Sized Data Buffers for Both Channel Status and UserData
- Two Audio Serial Ports (Ports A and B)
- Synchronous Serial Interface to External Signal Processors, Data Converters,and Logic
- Slave or Master Mode Operation With Sampling Rates Up to 216 kHz
- Supports Left-Justified, Right-Justified, and PhilipsI2S™ DataFormats
- Supports Audio Data Word Lengths Up to
- Four General-Purpose Digital Outputs
- Multifunction Programmable Through Control Registers
- Extensive Power-Down Support
- Functional Blocks May Be Disabled Individually When Not In Use
- Operates From 1.8-V Core and 3.3-V I/O Power Supplies
- Small TQFP-48 Package, Compatible With the SRC4382 and SRC4392
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Texas Instruments DIX4192IPFBRQ1
The DIX4192-Q1 device is a highly-integrated CMOS devicedesigned for use in professional and broadcast digital audio systems. The DIX4192-Q1 combines a digital audio interface receiver (DIR) and transmitter(DIT), two audio serial ports, and flexible distribution logic for interconnection of the functionblock data and clocks.
The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20 kHz to 216 kHz.
The DIX4192-Q1 device is configured using on-chip controlregisters and data buffers, which are accessed through either a four-wire serial peripheralinterface (SPI) port, or a two-wire I2C bus interface. Status registersprovide access to a variety of flag and error bits, which are derived from the various functionblocks. An open-drain interrupt output pin is provided, and is supported by flexible interruptreporting and mask options through control register settings. A master reset input pin is providedfor initialization by a host processor or supervisory functions.
The DIX4192-Q1 device requires a 1.8-V core logic supply,in addition to a 3.3-V supply for powering portions of the DIR, DIT, and line driver and receiverfunctions. A separate logic I/O supply supports operation from 1.65 V to 3.6 V, providingcompatibility with low-voltage logic interfaces typically found on digital signal processors andprogrammable logic devices.
The DIX4192-Q1 device is available in a lead-free, TQFP-48package.