|Package | PIN:||RHB | 32|
|Temp:||Q (-40 to 125)|
- AEC-Q100 Qualified for Automotive Applications
- Device Temperature Grade 1: –40°C to +125°C AmbientOperating Temperature
- Single H-Bridge Gate Driver
- Drives Four External N-Channel MOSFETs
- Supports 100% PWM Duty Cycle
- 5.5- to 45-V Operating Supply-Voltage Range
- Three Control-Interface Options
- PH/EN, Independent H-Bridge, and PWM
- Serial Interface for Configuration (DRV8703-Q1)
- Smart Gate Drive Architecture
- Adjustable Slew-Rate Control
- 10-mA to 260-mA Peak High-Side Source Current
- 20-mA to 440-mA Peak High-Side Sink Current
- 10-mA to 225-mA Peak Low-Side Source Current
- 20-mA to 430-mA Peak Low-Side Sink Current
- Independent Control of Each H-Bridge
- Supports 1.8-V, 3.3-V, and 5-V logic inputs
- Current-Shunt Amplifier
- Integrated PWM Current Regulation
- Low-Power Sleep Mode
- Small Package and Footprint
- 32-Pin VQFN
- 5 mm× 5 mm
- Wettable FlanksPackage
- Protection Features
- Supply Undervoltage Lockout (UVLO)
- Charge-Pump Undervoltage (CPUV) Lockout
- Overcurrent Protection (OCP)
- Gate-Driver Fault (GDF)
- ThermalShutdown (TSD)
- Watchdog Timer (DRV8703-Q1)
- Fault-Condition Output (nFAULT)
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Texas Instruments DRV8703QRHBRQ1
The DRV870x-Q1 devices are single H-bridge gate drivers that use fourexternal N-channel MOSFETs targeted to drive a bidirectional brushed-DC motor.
A PH/EN, independent H-Bridge, or PWM interface allows simpleinterfacing to controller circuits. An internal sense amplifier provides adjustable currentcontrol. Integrated Charge-Pump allows for 100% duty cycle support and can be used to driveexternal reverse battery switch.
Independent Half Bridge mode allows sharing of half bridges to controlmultiple DC motors sequentially in a cost-efficient way. The gate driver includes circuitry toregulate the winding current using fixed off-time PWM current chopping.
The DRV870x-Q1devices include Smart Gate Drive technology to remove the need for any external gate components(resistors and Zener diodes) while fully protecting the external FETs. The Smart Gate Drivearchitecture optimizes dead time to avoid any shoot-through conditions, provides flexibility inreducing electromagnetic interference (EMI) with programmable slew-rate control and protectsagainst any gate-short conditions. Additionally, active and passive pulldowns are included toprevent any dv/dt gate turnon.
A low-power sleep mode is provided which shuts down internal circuitry to achieve avery-low
quiescent-current draw. The device can be used in a very compact design because of its small5 mm × 5 mm package with few external components.