DS125BR401ANJYT

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DS125BR401ANJYT

Low-Power 12 Gbps 4-Lane Repeater With Equalization

Packaging

Package | PIN: NJY | 54
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $13.95
10-24 $12.97
25-99 $12.52
100-249 $10.93
250-499 $10.41
500-749 $9.58
750-999 $8.60
1000+ $8.57

Features

  • Low 65-mW/Channel (Typ) Power Consumption, With Option
    to Power Down Unused Channels
  • Linear Equalization allows for Link Training in PCIe and SAS
  • Supports Out-of-Band (OOB) Signaling
  • Advanced Signal Conditioning B-Side I/O
    • Receive CTLE up to 24 dB at 6 GHz
    • Transmit (Tx) DE > 10 dB
    • Tx Output Voltage: 700 mV to 1400 mV
  • Advanced Signal Conditioning A-Side I/O
    • Receive CTLE up to 10 dB at 6 GHz
    • Linear output drive
    • Output voltage range over 1200mV
  • Programmable via Terminal Selection, EEPROM, or
    SMBus Interface
  • Single Supply Voltage: 2.5 V or 3.3 V
  • −40°C to 85°C Operating Temperature Range
  • 4 kV HBM ESD Rating
  • Flow-Thru Layout in 10mmx5.5mm 54-Terminal Leadless
    WQFN Package

Texas Instruments  DS125BR401ANJYT

The DS125BR401A is an extremely low-power high-performance repeater/redriver designed to support four lanes carrying high speed interface up to 12 Gbps. The B-Side receiver’s continuous time linear equalizers (CTLE) provide high frequency boost of up to +24 dB at 6 GHz (12 Gbps) and are capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as backplane traces or twinaxial copper cables. The programmable equalization allows maximum flexibility in the physical placement within the interconnect channel. The A-Side channel has a 10 dB linear equalizer and linear output driver.

The A-Side channel has a settable 3-10 dB linear equalizer coupled to a linear output driver. When operating in SAS-3 and PCIe Gen-3 applications the DS125BR401A preserves transmit signal characteristics allowing the host controller and the end point to negotiate transmit equalizer coefficients. This transparency to the link training protocol aides system level interoperability and minimum latency.

The programmable settings can be applied easily via Terminals, software (SMBus or I2C), or loaded via an external EEPROM. In EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.