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DS125DF410SQE/NOPB

9.8 to 12.5 Gbps Quad Channel Retimer with Adaptive EQ, CDR and DFE

Packaging

Package | PIN: RHS | 48
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $23.72
10-24 $22.18
25-99 $21.48
100-249 $19.09
250-499 $18.95
500-749 $17.83
750-999 $16.00
1000+ $15.95

Features

  • Each Channel Independently Locks to Data Rates from 9.8 to 12.5 Gbps and Submultiples
  • Fast Lock Operation Based on Protocol-Select Mode
  • Low Latency (~300ps)
  • Adaptive Equalization up to 34-dB Boost at 5 GHz
  • Adjustable Transmit VOD: 600 to 1300 mVp-p
  • Adjustable Transmit De-emphasis to –15 dB
  • Typical Power Dissipation (EQ+DFE+CDR+DE): 180 mW/Channel
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection/Indicator
  • On-Chip Eye Monitor (EOM), PRBS Generator
  • Single 2.5-V ± 5% Power Supply
  • SMBus/EEPROM Configuration Modes
  • Operating Temperature Range of –40 to 85°C
  • WQFN 48-Pin 7-mm x 7-mm Package
  • Easy Pin Compatible Upgrade Between Repeater and Retimers
    • DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
    • DS100DF410(EQ+DFE+CDR+DE): 10.3125 Gbps
    • DS110RT410 (EQ+CDR+DE): 8.5–11.3Gbps
    • DS110DF410 (EQ+DFE+CDR+DE): 8.5–11.3 Gbps
    • DS125RT410(EQ+CDR+DE): 9.8–12.5 Gbps
    • DS125DF410 (EQ+DFE+CDR+DE): 9.8–12.5Gbps
    • DS100BR410 (EQ+DE): Up to 10.3125Gbps

All trademarks are the property of their respective owners.

Texas Instruments  DS125DF410SQE/NOPB

The DS125DF410 is four channel retimer with integrated signal conditioning. The deviceincludes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap DecisionFeedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver toenable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieveBER < 1×10-15.

Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associatedsub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25 MHz crystaloscillator clock is used to speed up the CDR lock process. This clock is not used for training thePLL and does not need to be synchronous with the serial data.

The programmable settings can be applied using the SMBus (I2C) interface, or they can beloaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-timemeasurement of high-speed serial data for system bring-up or field tuning.