|Package | PIN:||NEZ | 100|
|Temp:||S (-10 to 70)|
- Up to 6.384 Gbps Throughput
- 66MHz to 133MHz Input Clock Support
- Reduces Cable and Connector Size and Cost
- Pre‐Emphasis Reduces Cable Loading Effects
- DC Balance Reduces ISI Distortion
- 24 Bit Double Edge Inputs
- 3V Tolerant LVCMOS/LVTTL Inputs
- Low Power, 2.5V Supply
- Flow-Through Pinout
- In 100-Pin TQFP Package
- Conforms with TIA/EIA‐644-A LVDS Standard
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Texas Instruments DS90CR485VS/NOPB
The DS90CR485 serializes the 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phase-locked transmit clock is also in parallel with the data streams over a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and connector size and cost. The double edge input strobes data on both the rising and falling edges of the clock. This minimizes the pin count required and simplifies PCB routing between the host chip and the serializer.
This chip is an ideal solution to solve EMI and interconnect size problems for high throughput point-to-point applications.
The DS90CR485 is intended for use with the DS90CR486 Channel-Link receiver. It is also backward compatible with other Channel-Link receiver such as the DS90CR482 and DS90CR484.
For more details, please refer to the section of this datasheet.