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DS90UB933TRTVTQ1

12-bit 100 MHz FPD-Link III Serializer for 1MP/60fps and 2MP/30fps Cameras

Packaging

Package | PIN: RTV | 32
Temp: T (-40 to 105)
Carrier: Cut Tape
Qty Price
1-9 $10.62
10-24 $9.55
25-99 $8.92
100-249 $8.00
250-499 $7.47
500-749 $6.50
750-999 $5.62
1000+ $5.51

Features

  • AEC-Q100 Qualified for Automotive Applications With the Following Results:
    • Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature
  • 37.5-MHz to 100-MHz Input Pixel Clock Support
  • Robust Power-Over-Coaxial (PoC) Operation
  • Programmable Data Payload:
    • 10-Bit Payload up to 100-MHz
    • 12-Bit Payload up to 100-MHz
  • Continuous Low Latency Bidirectional Control Interface Channel with I2C Support at 400-kHz
  • Embedded Clock With DC-Balanced Coding to Support AC-Coupled Interconnects
  • Capable of Driving up to 15-m Coaxial or Shielded Twisted-Pair (STP) Cables
  • 4 Dedicated General-Purpose Input/Output (GPIO)
  • 1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputs on Serializer
  • Single Power Supply at 1.8-V
  • ISO 10605 and IEC 61000-4-2 ESD Compliant

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Texas Instruments  DS90UB933TRTVTQ1

The DS90UB933-Q1 device offers an FPD-Link III interface with a high-speed forwardchannel and a bidirectional control channel for data transmission over a single coaxial cable ordifferential pair. The DS90UB933-Q1 device incorporates differential signaling on both thehigh-speed forward channel and bidirectional control channel data paths. Theserializer/deserializer pair is targeted for connections between imagers and video processors in anelectronic control unit (ECU). This device is ideally suited for driving video data requiring up to12-bit pixel depth plus two synchronization signals along with bidirectional control channelbus.

Using TI’s embedded clock technology allows transparent full-duplex communication over asingle differential pair, carrying asymmetrical-bidirectional control channel information. Thissingle serial stream simplifies transferring a wide data bus over PCB traces and cable byeliminating the skew problems between parallel data and clock paths. This significantly savessystem cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector sizeand pins. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.