|Package | PIN:||RHS | 48|
|Temp:||I (-40 to 85)|
- Ultra-Low Noise, High Performance
- Jitter: 100-fs RMS Typical, FOUT > 100MHz
- PSNR: –80 dBc, Robust Supply Noise Immunity
- Flexible Device Options
- Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or AnyCombination
- Pin Mode, I2C Mode, EEPROMMode
- 71-Pin Selectable Pre-programmed Default Start-Up Options
- Dual Inputs With Automatic or Manual Selection
- Crystal Input: 10 to 52 MHz
- External Input: 1 to 300MHz
- Frequency Margining Options
- Fine Frequency Margining Using Low-Cost Pullable CrystalReference
- Glitchless Coarse Frequency Margining (%) Using OutputDividers
- Other Features
- Supply: 3.3-V Core, 1.8-V, 2.5-V, or 3.3-V OutputSupply
- Industrial Temperature Range (–40ºC to 85ºC)
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Texas Instruments LMK03318RHST
The LMK03318 device is an ultra-low-noise PLLATINUM™clock generator with one fractional-N frequency synthesizer with integrated VCO, flexible clockdistribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. Thedevice can generate multiple clocks for various multi-gigabit serial interfaces and digitaldevices, thus reducing BOM cost and board area and improving reliability by replacing multipleoscillators and clock distribution devices. The ultra-low jitter reduces bit-error rate (BER) inhigh-speed serial links.
For the PLL, a differential clock, a single-ended clock, or a crystal input can beselected as the reference clock. The selected reference input can be used to lock the VCO frequencyat an integer or fractional multiple of the reference input frequency. The VCO frequency can betuned between 4.8 GHz and 5.4 GHz. The PLL offers the flexibility to select a predefined oruser-defined loop bandwidth, depending on the needs of the application. The PLL has a post-dividerthat can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.
All the output channels can select the divided-down VCO clock from the PLL as the sourcefor the output divider to set the final output frequency. Some output channels can alsoindependently select the reference input for the PLL as an alternative source to be bypassed to thecorresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even orodd), output frequencies up to 1 GHz, and output phase synchronization capability.
All output pairs are ground-referenced CML drivers with programmable swing that can beinterfaced to LVDS, LVPECL, or CML receivers with AC coupling. All output pairs can also beindependently configured as HCSL outputs or 2 × 1.8-V LVCMOS outputs. The outputs offer lower powerat 1.8 V, higher performance and power supply noise immunity, and lower EMI compared tovoltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional3.3-V LVCMOS outputs can be obtained via the STATUS pins. This is an optional feature in case of aneed for 3.3-V LVCMOS outputs and device status signals are not needed.
The device features self start-up from on-chip programmable EEPROM or pre-defined ROMmemory, which offers multiple custom device modes selectable via pin control eliminating the needfor serial programming. The device registers and on-chip EEPROM settings are fully programmablethrough the I2C-compatible serial interface. The device slave address isprogrammable in EEPROM and LSBs can be set with a 3-state pin.
The device provides two frequency margining options with glitch-free operation to supportsystem design verification tests (DVT), such as standard compliance and system timing margintesting. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal onthe internal crystal oscillator (XO), and selecting this input as the reference to the PLLsynthesizer. The frequency margining range is determined by the trim sensitivity of the crystal andthe on-chip varactor range. XO frequency margining can be controlled through pin orI2C control for ease-of use and high flexibility. Coarse frequencymargining (in %) is available on any output channel by changing the output divide value viaI2C interface, which synchronously stops and restarts the output clockto prevent a glitch or runt pulse when the divider is changed.
Internal power conditioning provide excellent power supply noise rejection (PSNR),reducing the cost and complexity of the power delivery network. The analog and digital core blocksoperate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, or 3.3-V ± 5%supply.