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LMK03328RHST

Ultra-Low Jitter Clock Generator Family With Two Independent PLLs

Packaging

Package | PIN: RHS | 48
Temp: I (-40 to 85)
Carrier: Cut Tape
Qty Price
1-9 $16.77
10-24 $15.59
25-99 $15.05
100-249 $13.14
250-499 $12.51
500-749 $11.51
750-999 $10.33
1000+ $10.30

Features

  • Ultra Low Noise, High Performance
    • Jitter: 100-fs RMS Typical, FOUT > 100 MHz
    • PSNR: –80 dBc, Robust Supply Noise Immunity
  • Flexible Device Options
    • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or AnyCombination
    • Pin Mode, I2C Mode, and EEPROMMode
    • 71-Pin Selectable Pre-Programmed Default Start-Up Options
  • Dual Inputs With Automatic or Manual Selection
    • Crystal Input: 10 to 52 MHz
    • External Input: 1 to 300MHz
  • Frequency Margining Options
    • Fine Frequency Margining (±50 ppm Typical) Using Low-Cost Pullable CrystalReference
    • Glitchless Coarse Frequency Margining (%) Using OutputDividers
  • Other Features
    • Supply: 3.3-V Core, 1.8-V, 2.5-V, 3.3-V OutputSupply
    • Industrial Temperature Range (–40ºC to+85ºC)
    • Package: 7-mm × 7-mm 48-WQFN

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Texas Instruments  LMK03328RHST

The LMK03328 device is an ultra-low-noise clock generator with two fractional-Nfrequency synthesizers with integrated VCOs, flexible clock distribution and fanout, andpin-selectable configuration states stored in on-chip EEPROM. The device can generate multipleclocks for various multi-gigabit serial interfaces and digital devices, reduces BOM cost and boardarea, and improves reliability by replacing multiple oscillators and clock distribution devices.The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

For each PLL, a differential/single-ended clock or crystal input can be selected as thePLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at aninteger or fractional multiple of the reference input frequency. The VCO frequency for therespective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent inperformance and functionality. Each PLL offers the flexibility to select a predefined oruser-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-dividerthat can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.

All the output channels can select the divided-down VCO clock from PLL1 or PLL2 as thesource for the output divider to set the final output frequency. Some output channels can alsoindependently select the reference input for PLL1 or PLL2 as an alternative source to be bypassedto the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256(even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.

All output pairs are ground-referenced CML drivers with programmable swing that can beinterfaced to LVDS or LVPECL or CML receivers with AC coupling. All output pairs can also beindependently configured as HCSL outputs or 2x 1.8-V LVCMOS outputs. The outputs offer lower powerat 1.8 V, higher performance and power supply noise immunity, and lower EMI compared tovoltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional3.3-V LVCMOS outputs can be obtained through the STATUS pins. This is an optional feature in caseof a need for 3.3-V LVCMOS outputs and device status signals are not needed.

The device features self start-up from on-chip programmable EEPROM or pre-defined ROMmemory, which offers multiple custom device modes selectable through pin control and can eliminatethe need for serial programming. The device registers and on-chip EEPROM settings are fullyprogrammable via I2C-compatible serial interface. The device slaveaddress is programmable in EEPROM and LSBs are settable with a 3-state pin.

The device provides two frequency margining options with glitch-free operation to supportsystem design verification tests (DVT), such as standard compliance and system timing margintesting. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal onthe internal crystal oscillator (XO), and selecting this input as the reference to the PLLsynthesizer. The frequency margining range is determined by the crystal’s trim sensitivity and theon-chip varactor range. XO frequency margining can be controlled through pin orI2C control for ease-of-use and high flexibility. Coarse frequencymargining (in %) is available on any output channel by changing the output divide value throughI2C interface, which synchronously stops and restarts the output clockto prevent a glitch or runt pulse when the divider is changed.

Internal power conditioning provide excellent power supply noise rejection (PSNR),reducing the cost and complexity of the power delivery network. The analog and digital core blocksoperate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, 3.3-V ± 5%supply.